Synchronous and Asynchronous Counter

Synchronous Counter

In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses.  Thus, all the flip-flops change state simultaneously (in parallel).  The circuit below is a 3-bit synchronous counter.  The J and K inputs of FF0 are connected to HIGH.  FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1.

Asynchronous Counter

An asynchronous (ripple) counter is a single d-type flip-flop, with its J (data) input fed from its own inverted output. This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0). This counter will increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0. Notice that this creates a new clock with a 50% duty cycle at exactly half the frequency of the input clock. If this output is then used as the clock signal for a similarly arranged D flip-flop (remembering to invert the output to the input), one will get another 1 bit counter that counts half as fast.

Cycle	Q1	Q0	(Q1:Q0)dec
0	0	0	0
1	0	1	1
2	1	0	2
3	1	1	3
4	0	0	0

References: http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/counter05.html

http://en.wikipedia.org/wiki/Counter